The present invention relates to a computer architecture employing a hardware multiplier circuit, and in particular, to a multiplier circuit operating to change its accuracy during run time.
Achieving energy efficiency is important in mobile computing devices such as smart phones and tablets because of their reliance on battery power and the size and weight constraints of such devices which limit battery size and capacity. At the same time, such mobile computing devices are increasingly using sophisticated human machine interfaces (HMIs) relying on techniques such as speech recognition, handwriting recognition, and gesture recognition. Such “recognition” tasks may require large numbers of multiplication operations, for example, associated with matrix multiplication. Demands for high-speed multiplication are normally handled by specialized hardware multipliers. Such hardware multipliers may not be available or practical in portable devices because of their energy demands.